 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| ? semiconductor components industries, llc, 2016 september, 2016 ? rev. 12 1 publication order number ncp1239/d ncp1239 fixed frequency current\mode controller for flyback converter the ncp1239 is a fixed-frequency current-mode controller featuring a high-voltage start-up current source to provide a quick and lossless power-on sequence. this function greatly simplifies the design of the auxiliary supply and the v cc capacitor by activating the internal start-up current source to supply the controller during start-up, transients, latch, stand-by etc. with a supply range up to 35 v, the controller hosts a jittered 65 or 100-khz switching circuitry operated in peak current mode control. when the power on the secondary side starts to decrease, the controller automatically folds back its switching frequency down to minimum level of 26 khz. as the power further goes down, the part enters skip cycle while limiting the peak current that insures excellent efficiency in light load condition. ncp1239 features a timer-based fault detection circuitry that ensures a quasi-flat overload detection, independent of the input voltage. features ? fixed-frequency 65-khz or 100-khz current-mode control operation ? frequency foldback down to 26 khz and skip mode to maximize performance in light load conditions ? adjustable over power protection (opp) circuit ? high-voltage current source with brown-out (bo) detection ? internal slope compensation ? internal fixed soft-start ? frequency jittering in normal and frequency foldback modes ? 64-ms timer-based short-circuit protection with auto-recovery or latched operation ? pre-short ready for latched ocp versions ? latched ovp on vcc ? autorecovery for c and e versions ? latched ovp/otp input for improved robustness ? 35-v v cc operation ? 500 ma peak source/sink drive capability ? internal thermal shutdown ? extremely low no-load standby power ? pin-to-pin compatible with the existing ncp1236/1247 series ? these devices are pb-free and are rohs compliant typical applications ? ac-dc converters for tvs, set-top boxes and printers ? offline adapters for notebooks and netbooks marking diagram soic?7 case 751u www.onsemi.com pin connections 1239xfff = specific device code x = a, b, c, d, e, f, g, h or i fff = 065 or 100 a = assembly location l = wafer lot y = year w = work week = pb?free package 1239xfff alywx 1 8 hv vcc drv fault fb cs gnd ordering information 8 6 5 1 3 4 2 see detailed ordering and shipping information on page 25 o f this data sheet.
ncp1239 www.onsemi.com 2 figure 1. application schematic (opp adjustment) ncp1239 vbulk . . opp adjsut. vout ovp . 1 2 6 45 8 3 ntc table 1. pin function description pin no. pin name description 1 fault the controller enters fault mode if the voltage of this pin is pulled above or below the fault thresholds. a precise pull up current source allows direct interface with an ntc thermistor. fault detection triggers a latch. 2 fb hooking an optocoupler collector to this pin will allow regulation. 3 cs this pin monitors the primary peak current but also offers an overpower compensation adjustment. when the cs pin is brought above 1.2 v, the part is permanently latched off. 4 gnd the controller ground. 5 drv the driver?s output to an external mosfet gate. 6 vcc this pin is connected to an external auxiliary voltage. an ovp comparator monitors this pin and offers a means to latch the converter in fault conditions. 7 nc non-connected for improved creepage distance. 8 hv connected to the bulk capacitor or rectified ac line, this pin powers the internal current source to deliver a start- up current. it is also used to provide the brown-out detection and the hv sensing for the overpower protection. ncp1239 www.onsemi.com 3 table 2. device option and designations device frequency ocp protection ocp timer v cc ovp threshold v cc ovp protection fault pin protection bo levels bo timer soft? start timer ncp1239ad65r2g 65 khz latch 64 ms 25.5 v latch latch 110 / 101 68 ms 8 ms ncp1239bd65r2g 65 khz auto? recovery 64 ms 25.5 v latch latch 110 / 101 68 ms 8 ms ncp1239cd65r2g 65 khz auto? recovery 64 ms 25.5 v auto? recovery latch 110 / 101 68 ms 8 ms ncp1239dd65r2g 65 khz auto? recovery 64 ms 25.5 v latch latch 101 / 95 68 ms 8 ms ncp1239ed65r2g 65 khz auto? recovery 64 ms 25.5 v auto? recovery auto? recovery 110 / 101 68 ms 8 ms ncp1239fd65r2g 65 khz latch 64 ms 32 v latch latch 229 / 176 68 ms 4 ms ncp1239hd65r2g 65 khz latch 64 ms 25.5 v latch latch 229 / 224 68 ms 8 ms ncp1239id65r2g 65 khz latch 128 ms 25.5 v latch latch 101 / 95 68 ms 4 ms ncp1239ad100r2g 100 khz latch 64 ms 25.5 v latch latch 110 / 101 68 ms 8 ms ncp1239bd100r2g 100 khz auto? recovery 64 ms 25.5 v latch latch 110 / 101 68 ms 8 ms NCP1239ED100R2G 100 khz auto? recovery 64 ms 25.5 v auto? recovery auto? recovery 110 / 101 68 ms 8 ms ncp1239gd100r2g 100 khz latch 64 ms 25.5 v latch latch 95 / 86 136 ms 8 ms ncp1239 www.onsemi.com 4 figure 2. simplified block diagram vcc drv leb gnd cs fb hv dual hv startup current source hv sample 600?ns time constant up counter 4 rst ovp/otp gone? fault vfault(clamp) vfault(otp) vfault(ovp) iotp option for ovp_vcc up counter 4 rst vlimit2 leb 120 ns 300 ns vlimit1 soft?start ramp 8 ms ss end vdd / 4 rup vskip overcurrent soft?start pwm oscillator 65 khz / 100 khz compensation slope stop foldback jitter s r q q ocp_flag pwm ocp timer 64 ms ocp_flag skip hv detection & sampling bo vcc logic management 20us time constant tsd vcc(ovp) ovp_vcc ovp_vcc (option) vdd vdd vcc(reset) uvlo s r q q vcc(reset) latch protection mode reset vcc(reset) timer 1 s auto?recovery s r q q clamp clock bo latch tsd skip clock + nc bo end bo end uvlo vdd ibias ocp fault gone? bo tsd tsd end iopp hv sample dmax opp current generation ncp1239 www.onsemi.com 5 table 3. maximum ratings rating symbol value unit power supply voltage, v cc pin, continuous voltage v cc ?0.3 to 35 v maximum voltage on low power pins cs, fb and fault ?0.3 to 5.5 v maximum voltage on drv pin v drv ?0.3 to 20 v high voltage pin hv ?0.3 to 650 v thermal resistance junction-to-air single layer pcb 25 mm , 2 oz cu printed circuit copper clad r j?a 250 c/w maximum junction temperature t j(max) 150 c storage temperature range tstg ?60 to 150 c esd capability (note 2) human body model ? all pins except hv machine model esd hbm esd mm 4 200 kv v charged-device model esd capability per jedec jesd22?c101e 1 kv moisture sensitivity level msl 1 stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. refer to electrical characteristics, recommended operating ranges and/or application information for safe operating parameters. 2. this device series incorporates esd protection and is tested by the following methods: esd human body model tested per jedec jesd22?a114f esd machine model tested per jedec jesd22?a115c charged-device model esd capability tested per jedec jesd22?c101e latch-up current maximum rating: 150 ma per jedec standard: jesd78 table 4. electrical characteristics (for typical values t j = 25 c, for min/max values t j = ?40 c to +125 c, v hv = 125 v, v cc = 11 v unless otherwise noted) parameter test conditions symbol min typ max unit start-up section minimum voltage for current source operation i hv = 90% i start2 , v cc = v cc(on) ? 0.5 v v hv(min) ? 25 60 v current flowing out of v cc pin v cc = 0 v i start1 0.2 0.5 0.8 ma current flowing out of v cc pin v cc = v cc(on) ? 0.5 v i start2 1.5 3 4.5 ma hv pin leakage current v hv = 325 v i leak1 ? 8 20 a supply section start-up threshold hv current source stop threshold v cc increasing v cc(on) 11.0 12.0 13.0 v hv current source restart threshold v cc decreasing v cc(min) 9.0 10.0 11.0 v minimum operating voltage v cc decreasing v cc(off) 8.0 8.8 9.4 v operating hysteresis v cc(on) = v cc(off) v cc(hys) 3.0 ? ? v v cc level for i start1 to i start2 transition v cc(inhibit) 0.7 1.2 1.7 v v cc level where logic functions are reset v cc decreasing v cc(reset) 6.5 7 7.5 v internal ic consumption v fb = 3.2 v, f sw = 65 khz and c l =0 icc1 ? 1.4 2.2 ma internal ic consumption v fb = 3.2 v, f sw = 65 khz and c l =1nf icc2 ? 2.1 3.0 ma internal ic consumption v fb = 3.2 v, f sw = 100 khz and c l =0 icc1 ? 1.7 2.5 ma product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 1. guaranteed by design 2. cs pin source current is a sum of i bias and i opp , thus at v hv = 125 v is observed the i bias only, because i opc is switched off. ncp1239 www.onsemi.com 6 table 4. electrical characteristics (continued) (for typical values t j = 25 c, for min/max values t j = ?40 c to +125 c, v hv = 125 v, v cc = 11 v unless otherwise noted) parameter unit max typ min symbol test conditions supply section internal ic consumption v fb = 3.2 v, f sw = 100 khz and c l = 1 nf icc2 ? 3.1 4.0 ma internal ic consumption in skip cycle v cc = 12 v, v fb = 0.775 v driving 8 a/650 v mosfet icc(stb) ? 500 ? a internal ic consumption in fault mode fault or latch icc3 ? 400 ? a internal ic consumption before start-up v cc(min) < v cc < v cc(on) icc4 ? 310 ? a internal ic consumption before start-up v cc < v cc(min) icc5 ? 20 ? a drive output rise time (10?90%) v drv from 10 to 90% v cc = v cc(off) + 0.2 v, c l = 1 nf t r ? 40 ? ns fall time (90?10%) v drv from 90 to 10% v cc = v cc(off) + 0.2 v, c l = 1 nf t f ? 30 ? ns source resistance r oh ? 6 ? sink resistance r ol ? 6 ? peak source current drv high state, v drv = 0 v (note 1) v cc = v cc(off) + 0.2 v, c l = 1 nf i source ? 500 ? ma peak sink current drv low state, v drv = v cc (note 1) v cc = v cc(off) + 0.2 v, c l = 1 nf i sink ? 500 ? ma high state voltage (low v cc level) v cc = 9 v, r drv = 33 k drv high state v drv(low) 8.8 ? ? v high state voltage (high v cc level) v cc = v cc(ovp) ? 0.2 v, drv high state and unloaded v drv(clamp) 11.0 13.5 16.0 v current comparator input pull-up current v cs = 0.7 v i bias ? 1 ? a maximum internal current setpoint t j from ?40 c to +125 c (no opp) v limit1 0.752 0.800 0.848 v abnormal over-current fault threshold t j = +25 c (no opp) v limit2 1.10 1.20 1.30 v default internal voltage set point for frequency foldback trip point ~59% of v limit v fold(cs) ? 475 ? mv internal peak current setpoint freeze ~31% of v limit v freeze(cs) ? 250 ? mv propagation delay from v limit detection to gate off-state drv output unloaded t del ? 50 100 ns leading edge blanking duration t leb1 ? 300 ? ns abnormal over-current fault blanking duration for v limit3 t leb2 ? 120 ? ns number of clock cycles before fault confirmation t count ? 4 ? product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 1. guaranteed by design 2. cs pin source current is a sum of i bias and i opp , thus at v hv = 125 v is observed the i bias only, because i opc is switched off. ncp1239 www.onsemi.com 7 table 4. electrical characteristics (continued) (for typical values t j = 25 c, for min/max values t j = ?40 c to +125 c, v hv = 125 v, v cc = 11 v unless otherwise noted) parameter unit max typ min symbol test conditions current comparator internal soft-start duration activated upon startup or auto?recovery a, b, c, d, e, g, h versions f and i versions t ss ? ? 8 4 ? ? ms internal oscillator oscillation frequency (65-khz version) f osc 60 65 70 khz oscillation frequency (100-khz version) f osc 92 100 108 khz maximum duty-cycle d max 76 80 84 % frequency jittering in percentage of f osc ? jitter is kept even in foldback mode f jitter ? 5 ? % swing frequency f swing ? 240 ? hz feedback section equivalent ac resistor from fb to gnd (note 1) r eq ? 25 ? k internal pull-up voltage on fb pin fb open v fb(ref) 4.1 4.3 ? v v fb to current setpoint division ratio k fb ? 4 ? feedback voltage below which the peak current is frozen v freeze ? 1.0 ? v frequency foldback frequency foldback level on fb pin 59% of maximum peak current v fold ? 1.90 ? v transition frequency below which skip-cycle occurs v fb =v skip + 0.5 v f trans 22 26 30 khz end of frequency foldback feedback level f sw = f min v fold(end) ? 1.50 ? v skip-cycle level voltage on fb pin v skip ? 0.80 ? v hysteresis on the skip comparator (note 1) v skip(hyst) ? 30 ? mv internal ramp compensation compensation ramp slope f sw = 65 khz, r up = 30 k f sw = 100 khz, r up = 30 k s 65 s 100 ? ? ?29 ?45 ? ? mv/ s overpower compensation (opp) v hv to i opp conversion ratio k opp ? 0.54 ? a/v current flowing out of cs pin (note 2) v hv = 125 v v hv = 162 v v hv = 328 v v hv = 365 v i opp(125) i opp(162) i opp(328) i opp(365) ? ? ? 105 0 20 110 130 ? ? ? 150 a percentage of applied opp current v fb < v fold i opp1 ? 0 ? % percentage of applied opp current v fb > v fold + 0.7 v (v opp ) i opp2 ? 100 ? % clamped opp current v hv > 365 v i opp3 105 130 150 a watchdog timer for dc operation t wd(opp) ? 32 ? ms brown-out (bo) brown-out thresholds (a, b, c & e versions) v hv increasing v bo(on) 100 110 120 v brown-out thresholds (a, b, c & e versions) v hv decreasing v bo(off) 93 101 109 v product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 1. guaranteed by design 2. cs pin source current is a sum of i bias and i opp , thus at v hv = 125 v is observed the i bias only, because i opc is switched off. ncp1239 www.onsemi.com 8 table 4. electrical characteristics (continued) (for typical values t j = 25 c, for min/max values t j = ?40 c to +125 c, v hv = 125 v, v cc = 11 v unless otherwise noted) parameter unit max typ min symbol test conditions brown-out (bo) brown-out thresholds (d and i versions) v hv increasing v bo(on) 92 101 110 v brown-out thresholds (d and i versions) v hv decreasing v bo(off) 87 95 103 v brown-out thresholds (f version only) v hv increasing v bo(on) 211 229 247 v brown-out thresholds (f version only) v hv decreasing v bo(off) 164 176 188 v brown-out thresholds (g version only) v hv increasing v bo(on) 86 95 104 v brown-out thresholds (g version only) v hv decreasing v bo(off) 79 86 93 v brown-out thresholds (h version only) v hv increasing v bo(on) 221 229 247 v brown-out thresholds (h version only) v hv decreasing v bo(off) 208 224 240 v brown-out timer duration (a, b, c, d, e, f, h and i versions) v hv decreasing t bo 54 68 82 ms brown-out timer duration (g version only) v hv decreasing t bo 110 136 162 ms fault input (otp/ovp) over-voltage protection threshold v fault increasing v fault(ovp) 2.8 3.0 3.2 v over-temperature protection threshold v fault decreasing v fault(otp) 0.37 0.40 0.43 v ntc biasing current v fault = 0 v i otp 39 45 51 a additional ntc biasing current during soft-start only v fault = 0 v ? during soft-start only i otp_boost 38 44 50 a latch clamping voltage i fault = 0 ma v fault(clamp)0 1.1 1.35 1.6 v latch clamping voltage i fault = 1 ma v fault(clamp)1 2.2 2.7 3.2 v blanking time after drive turn off t latch(blank) ? 1 ? s number of clock cycles before latch confirmation t latch(count) ? 4 ? over-current protection (ocp) internal ocp timer duration a, b, c, d, e, f, g and h versions t ocp 51 64 77 ms internal ocp timer duration i version only t ocp 102 128 154 ms auto-recovery timer t autorec 0.85 1 1.35 s v cc over-voltage (v cc ovp) latched over voltage protection on v cc pin a, b, c, d, e, g and h versions v cc(ovp) 24.0 25.5 27.0 v latched over voltage protection on v cc pin f version only v cc(ovp) 30.0 32.0 34.0 v delay before ovp on v cc confirmation t ovp(delay) ? 20 ? s thermal shutdown (tsd) temperature shutdown t j increasing (note 1) t shdn 135 150 165 c temperature shutdown hysteresis t j decreasing (note 1) t shdn(hys) ? 20 ? c product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 1. guaranteed by design 2. cs pin source current is a sum of i bias and i opp , thus at v hv = 125 v is observed the i bias only, because i opc is switched off. ncp1239 www.onsemi.com 9 figure 3. v cc(on) vs. junction temperature figure 4. v cc(min) vs. junction temperature temperature ( c) 80 60 40 20 0 v cc(on) (v) ?40 12.5 12.0 11.5 11.0 13.0 typical performance characteristics figure 5. v cc(off) vs. junction temperature figure 6. v cc(inhibit) vs. junction temperature figure 7. icc2 (65-khz version) vs. junction temperature figure 8. icc2 (100-khz version) vs. junction temperature ?20 100 120 temperature ( c) 80 60 40 20 0 v cc(min) (v) ?40 10.5 10.0 9.5 9.0 11.0 ?20 100 120 temperature ( c) 80 60 40 20 0 v cc(off) (v) ?40 9.2 8.8 8.4 8.0 ?20 100 120 temperature ( c) 80 60 40 20 0 v cc(inhibit) (v) ?40 1.3 1.1 0.9 0.7 ?20 100 120 1.7 1.5 temperature ( c) 80 60 40 20 0 icc2 (ma) ?40 2.6 2.2 1.8 1.4 ?20 100 120 3.0 temperature ( c) 80 60 40 20 0 icc2 (ma) ?40 2.8 2.4 2.0 1.6 ?20 100 120 3.2 3.6 4.0 ncp1239 www.onsemi.com 10 figure 9. i start1 vs. junction temperature figure 10. i start2 vs. junction temperature temperature ( c) 80 60 40 20 0 i start1 (ma) ?40 0.5 0.4 0.3 0.2 0.6 typical performance characteristics figure 11. i leak1 vs. junction temperature figure 12. v limit1 vs. junction temperature figure 13. v limit2 vs. junction temperature figure 14. t del vs. junction temperature ?20 100 120 temperature ( c) 80 60 40 20 0 i start2 (ma) ?40 3.0 2.5 2.0 1.5 3.5 ?20 100 120 temperature ( c) 80 60 40 20 0 i leak1 ( a) ?40 12 8 4 0 ?20 100 120 temperature ( c) 80 60 40 20 0 v limit1 (v) ?40 0.82 0.80 0.78 0.76 ?20 100 120 0.84 temperature ( c) 80 60 40 20 0 v limit2 (v) ?40 1.25 1.20 1.15 1.10 ?20 100 120 1.30 temperature ( c) 80 60 40 20 0 t del (ns) ?40 25 20 15 10 ?20 100 120 30 35 40 0.7 0.8 4.0 4.5 24 20 16 ncp1239 www.onsemi.com 11 figure 15. t leb1 vs. junction temperature figure 16. t leb2 vs. junction temperature temperature ( c) 80 60 40 20 0 t leb1 (ns) ?40 260 220 180 140 300 typical performance characteristics figure 17. t ss vs. junction temperature figure 18. f osc (65-khz version) vs. junction temperature figure 19. f osc (100-khz version) vs. junction temperature figure 20. d max vs. junction temperature ?20 100 120 temperature ( c) 80 60 40 20 0 t leb2 (ns) ?40 100 80 60 40 120 ?20 100 120 temperature ( c) 80 60 40 20 0 t ss (ms) ?40 7 6 ?20 100 120 temperature ( c) 80 60 40 20 0 f osc (khz) ?40 66 64 62 60 ?20 100 120 68 temperature ( c) 80 60 40 20 0 f osc (khz) ?40 104 100 96 92 ?20 100 120 108 temperature ( c) 80 60 40 20 0 d max (%) ?40 82 80 78 76 ?20 100 120 84 340 380 10 9 8 70 ncp1239 www.onsemi.com 12 figure 21. r eq vs. junction temperature figure 22. i oop3 vs. junction temperature temperature ( c) 80 60 40 20 0 r eq (k ) ?40 24 23 22 21 25 typical performance characteristics figure 23. v bo(on) vs. junction temperature figure 24. v bo(off) vs. junction temperature figure 25. t bo vs. junction temperature figure 26. v fault(ovp) vs. junction temperature ?20 100 120 temperature ( c) 80 60 40 20 0 i oop3 ( a) ?40 140 130 120 110 150 ?20 100 120 temperature ( c) 80 60 40 20 0 v bo(on) (v) ?40 104 100 ?20 100 120 temperature ( c) 80 60 40 20 0 v bo(off) (v) ?40 105 101 97 93 ?20 100 120 temperature ( c) 80 60 40 20 0 t bo (ms) ?40 78 70 62 54 ?20 100 120 82 temperature ( c) 80 60 40 20 0 v fault(ovp) (v) ?40 3.1 3.0 2.9 2.8 ?20 100 120 3.2 26 120 112 108 109 116 74 66 58 ncp1239 www.onsemi.com 13 figure 27. v fault(otp) vs. junction temperature figure 28. i otp vs. junction temperature temperature ( c) 80 60 40 20 0 v fault(otp) (v) ?40 0.40 0.39 0.38 0.37 0.41 typical performance characteristics figure 29. t ocp vs. junction temperature figure 30. t autorec vs. junction temperature figure 31. v cc(ovp) vs. junction temperature ?20 100 120 temperature ( c) 80 60 40 20 0 i otp ( a) ?40 45 43 41 39 51 ?20 100 120 temperature ( c) 80 60 40 20 0 t ocp (ms) ?40 61 57 ?20 100 120 temperature ( c) 80 60 40 20 0 t autorec (s) ?40 1.1 1.0 0.9 0.8 ?20 100 120 temperature ( c) 80 60 40 20 0 v cc(ovp) (v) ?40 26.0 25.0 24.0 ?20 100 120 27.0 0.43 73 69 65 1.3 26.5 25.5 24.5 0.42 49 47 1.2 ncp1239 www.onsemi.com 14 definition general the ncp1239 implements a standard current mode architecture where the switch-off event is dictated by the peak current setpoint. this component represents the ideal candidate where low part-count and cost effectiveness are the key parameters, particularly in low-cost ac-dc adapters, open-frame power supplies etc. the ncp1239 packs all the necessary components normally needed in today modern power supply designs, bringing several enhancements such as a non-dissipative over power protection (opp), a brown-out protection or hv start-up current source. current-mode operation with internal ramp compensation implementing peak current mode control operating at a 65 or 100-khz switching frequency, the ncp1239 offers a fixed internal compensation ramp that can easily by summed up to the sensed current. the controller can be used in ccm applications with wide input voltage range thanks to its fixed ramp compensation that prevents the appearance of sub-harmonic oscillations internal brown-out protection a portion of the bulk voltage is internally sensed via the high-voltage pin monitoring (pin 8). when the voltage on this pin is too low, the part stops pulsing. no re-start attempt is made until the controller senses that the voltage is back within its normal range. when the brown-out comparator senses the voltage is acceptable, de-latch occurs and the controller authorizes a re-start synchronized with v cc(on) . adjustable overpower compensation the high input voltage sensed on the hv pin is converted into a current. this current builds an off set superimposed on the current sense voltage which is proportional to the input voltage. by choosing the resistance value in series with the cs pin, the amount of compensation can be adjusted to the application. high-voltage start-up low standby power results cannot be obtained with the classical resistive start-up network. in this part, a high-voltage current-source provides the necessary current at start-up and turns off afterwards. emi jittering an internal low-frequency modulation signal varies the pace at which the oscillator frequency is modulated. this helps spreading out energy in conducted noise analysis. to improve the emi signature at low power levels, the jittering will not be disabled in frequency foldback mode (light load conditions). frequency foldback capability a continuous flow of pulses is not compatible with no-load/light-load standby power requirements. to excel in this domain, the controller observes the feedback pin and when it reaches a level of 1.9 v, the oscillator starts to reduce its switching frequency as the feedback level continues to decrease. when the feedback level reaches 1.5 v, the frequency hits its lower stop at 26 khz. when the feedback pin goes further down and reaches 1.0 v, the peak current setpoint is internally frozen. below this point, if the power continues to drop, the controller enters classical skip-cycle mode at a 31% frozen peak current. internal soft-start a soft-start precludes the main power switch from being stressed upon start-up. in this controller, the soft-start is internally fixed to 8 ms. soft-start is activated when a new start-up sequence occurs or during an auto-recovery hiccup. fault input the ncp1239 includes a dedicated fault input accessible via its fault pin (pin 1). it can be used to sense an over-voltage condition on the adapter. the circuit can be latched off by pulling the pin above the upper fault threshold, v fault(ovp) , typically 3.0 v. the controller is also disabled if the fault pin voltage, v fault , is pulled below the lower fault threshold, v fault(otp) , typically 0.4 v. the lower threshold is normally used for detecting an over -temperature fault (by the means of an ntc). ovp protection on v cc it is sometimes interesting to implement a circuit protection by sensing the v cc level. this is what this controller does by monitoring its v cc pin. when the voltage on this pin exceeds v cc(ovp) threshold, the pulses are immediately stopped and the part enters in an endless hiccup or auto-recovery mode depending on controller options. short-circuit/overload protection short-circuit and especially overload protections are difficult to implement when a strong leakage inductance between auxiliary and power windings affects the transformer (the aux winding level does not properly collapse in presence of an output short). here, every time the internal 0.8-v maximum peak current limit is activated, an error flag is asserted and a time period starts, thanks to the 64-ms timer. when the fault is validated, all pulses are stopped and the controller enters an auto-recovery burst mode, with a soft-start sequence at the beginning of each cycle. an internal timer keeps the pulses off for 1 s typically which, associated to the 64-ms pulsing re-try period, ensures a duty-cycle in fault mode less than 10%, independent from the line level. as soon as the fault disappears, the smps resumes operation. please note that some version offers an auto-recovery mode (b, c, d and e versions) as we just described, some do not and latch off in case of a short-circuit (a, f, g, h and i versions). ncp1239 www.onsemi.com 15 hv current source pin the ncp1239 hv circuitry provides three features: ? start-up current source to charge the v cc capacitor at power on ? brown-out protection: when the hv pin voltage is below v bo(off) for the 68-ms blanking time (136 ms for g version), the ncp1239 stops operating and recovers whenthe hv pin voltage exceeds v bo(on) ? over power protection: hv pin voltage is sensed to determine the amount of opp current flowing out the cs pin the hv pin can be connected either to the bulk capacitor or to the input line terminals through a diode. it is further recommended to implement one or two resistors (in the range of 2.2 k ) to reduce the noise that can be picked-up by the hv pin. start-up sequence the start-up time of a power supply largely depends on the time necessary to charge the v cc capacitor to the controller start-up threshold (v cc(on) which is 12 v typically). the ncp1239 high-voltage current-source provides the necessary current for a prompt start-up and turns off afterwards. the delivered current (i start1 ) is reduced to less than 0.5 ma when the v cc voltage is below v cc(inhibit) (1.2 v typically). this feature reduces the die stress if the v cc pin happens to be accidentally grounded. when v cc exceeds v cc(inhibit), a 3-ma current (i start2 ) is provided and charges the v cc capacitor. please note that the internal ic consumption is increased from few a to 310 a (icc4) when v cc crosses v cc(min) in order to have internal logic wake-up when v cc reaches v cc(on) . the v cc charging time is then the total of the three following durations: ? charge from 0 v to v cc(inhibit) : t start1 v cc(inhibit) c v cc i start1 icc5 (eq. 1) ? charge from v cc(inhibit) to v cc(min) : t start2 v cc(min) v cc(inhibit) c v cc i start2 icc5 (eq. 2) ? charge from v cc(min) to v cc(on) : t start3 v cc(on) v cc(min) c v cc i start2 icc4 (eq. 3) assuming a 22- f v cc capacitor is selected and replacing i start1 , i start2 , icc4, icc5, v cc(inhibit) and v cc(on) by their typical values, it comes: t start1 12 22 u 500 u 20 u 55 ms (eq. 4) t start2 ( 10 1.2 ) 22 u 3m 20 u 65 ms (eq. 5) t start3 ( 12 10) 22 u 3m 310 u 16 ms (eq. 6) t start t start1 t start2 t start3 136 ms (eq. 7) figure 32. the v cc at start-up is made of two segments given the short-circuit protection implemented on the hv source t start1 t start2 t start3 v cc (t) v cc(on) v cc(inhibit) v cc(min) ncp1239 www.onsemi.com 16 if the v cc capacitor is first dimensioned to supply the controller for the traditional 5 to 50 ms until the auxiliary winding takes over, no-load standby requirements usually cause it to be larger. the hv start-up current source is then a key feature since it allows keeping short start-up times with large v cc capacitors (the total start-up sequence duration is often required to be less than 1 s). brown-out circuitry for the vast majority of controllers, input line sensing is performed via a resistive network monitoring the bulk voltage or the incoming ac signal. when in the quest of low standby power, the external network adds a consumption burden and deteriorates the power supply standby power performance. owing to its proprietary high-voltage technology, on semiconductor now offers onboard line sensing without using an external network. the system includes a 90-m resistive network that brings a minimum start-up threshold and an auto-recovery brown-out protection. both levels are independent from the input voltage ripple. the brown-out thresholds are fixed (see levels in the electrical characteristics table), but they are designed to fit most of standard ac-dc converter applications. the simplified internal schematic appears in figure 33 while typical operating waveforms are drawn in figure 34 and figure 35. figure 33. a simplified view of the brown-out circuitry l1 n emi filter vbulk rbo_h rbo_l hv gnd bo_ok vbo when the hv pin voltage drops below the v bo(off) threshold, the brown-out protection trips: the controller stops generating drv pulses once the bo timer elapses. v cc is discharged to v cc(min) by the controller consumption itself. when this level is reached, the hv current source is activated to lifts v cc up again. at new v cc(on) , bo signal is again sensed. if v hv >v bo(on) , the parts restarts. if the condition is not met, no drive pulse is delivered and internal ic consumption brings v cc down again. as a result, v cc operates in hiccup mode during a bo event. ncp1239 www.onsemi.com 17 figure 34. bo event during normal operation bo_ok = "0" drive pulse stops v cc(on) v cc(off) v cc(min) v cc (t) bo(t) bo_ok = "0" bo_ok = "1" t t v drv (t) no pulse area bo_ok = "1" v cc hiccup waiting bo signal figure 35. bo event before start-up bo no ok no drive pulse bo_ok = "1" wait the next v cc(on) for fresh start-up sequence v cc(on) v cc(off) v cc(min) first drive pulse v cc (t) v cc hiccup waiting bo signal v cc(inhibit) bo(t) bo_ok = "0" bo_ok = "1" t t ncp1239 www.onsemi.com 18 over power protection over power protection (opp) is a known means to limit the output power runaway at high mains. several elements such as propagation delays and operating mode explain why a converter operated at high line delivers more power than at low line. ncp1239 senses the input voltage via hv pin. this line voltage is transformed into a current information further applied to the current sense pin (cs). a resistor placed in series from the sense resistor to the cs pin will create an offset voltage proportional to the input voltage variation. an added current sink will ensure a zero opp current at low line (125 v dc), leaving the converter power capability intact in the lowest operating voltage. figure 36 presents the internal simplified architecture of this opp circuitry. figure 36. over power protection is provided via the bulk voltage present on hv pin cs hv sample & sampling hv detection hv ropp rsense offset to c s comparator l1 n emi filter vbulk iopp opp current generation vfb the hv voltage will be transformed into a current equal to 67.5 a when the hv pin is biased to 125 v. however, there is an internal fixed sink of 67.5 a. therefore, the net current flowing into r opp is 0 at this low-voltage input ( 125 v dc), ensuring an almost non-compensated converter at low line: at a 115-v rms input (162 v dc), the current from the ota block will induce a 87.5- a current, turning into a 20- a offset current flowing into r opp . now, assume a 260-v rms input voltage (365 v dc), the controller will generate an offset current of: 365 0.54 u 67.5 u 130 a (eq. 8) assume we need to reduce the maximum peak current setpoint by 250 mv to limit the maximum power at the considered 260-v rms input. in that case, we will need to generate a 250-mv offset across r opp . with a 130- a current, r opp should be equal to: 250 m 130 u 192 k (eq. 9) a small 100?220-pf capacitor closely connected between the cs and gnd pins will form an effective noise filter and nicely improves the converter immunity. now, with this 1.92-k resistance, the low-line 20- a offset current will incur a 38-mv drop, which, in relationship to a 800-mv maximum peak, generates a small 5% reduction. assuming a full dcm operation, the power would be reduced by 0.95 2 or 9.75% only. please note that the opp current is clamped for a hv pin voltage greater than 365 v dc. should you lift the pin above this voltage, there will be no increase of the opp current. the offset voltage can affect the standby power performance by reducing the peak current setpoint in light-load conditions. for this reason, it is desirable to cancel ncp1239 www.onsemi.com 19 its action as soon as frequency folback occurs. a typical curve variation is shown in figure 37. at low power, below the frequency folback starting point, 100% of the opp current is internally absorbed and no offset is created through the cs pin. when feedback increases again and reaches the frequency foldback point, as the frequency goes up, opp starts to build up and reaches its full value at v fold + 0.7 v. figure 37. the opp current is applied when the feedback voltage exceeds the folback point. it is 0 below it + 0.7 v v fold v fb (t) t t i opp (%) 100 0 max f sw decreases f sw increases fault input the ncp1239 includes a dedicated fault input accessible via the fault pin. figure 38 shows the architecture of the fault input. the controller can be latched by pulling up the pin above the upper fault threshold, v fault(ovp) , typically 3.0 v. an active clamp prevents the fault pin voltage from reaching the v fault(ovp) if the pin is open. to reach the upper threshold, the external pull-up current has to be higher than the pull-down capability of the clamp. v fault(ovp) v fault(clamp) r fault(clamp) 3v 1.35 v 1.35 k , (eq. 10) i.e. approximately 1.2 ma this function is typically used to detect a v cc or auxiliary winding over-voltage by means of a zener diode generally in series with a small resistor (see figure 38). neglecting the resistor voltage drop, the ovp threshold is then: v aux(ovp) v z v fault(ovp) (eq. 11) where v z is the zener diode voltage. the controller can also be latched off if the fault pin voltage, v fault , is pulled below the lower fault threshold, v fault(otp) , typically 0.4 v. this capability is normally used for detecting an over-temperature fault by means of an ntc thermistor. a pull up current source i otp , (typically 45 a) generates a voltage drop across the thermistor. the resistance of the ntc thermistor decreases at higher temperatures resulting in a lower voltage across the thermistor. the controller detects a fault once the thermistor voltage drops below v fault(otp) . the circuit detects an over-temperature situation when: r ntc i otp v fault(otp) (eq. 12) hence, the otp protection trips when r ntc v fault(otp) i otp 8.9 k (typically) (eq. 13) ncp1239 www.onsemi.com 20 the controller bias current is reduced during power up by disabling most of the circuit blocks including i fault(otp) . this current source is enabled once v cc reaches v cc(min) . a bypass capacitor is usually connected between the fault and gnd pins. it will take some time for v fault to reach its steady state value once i otp is enabled. therefore, the lower fault comparator (i.e. over-temperature detection) is ignored during soft-start. in addition, in order to speed up this fault pin capacitor, otp current is doubled during the soft-start period. figure 38. fault detection schematic fault ntc vaux latch s r q q up counter 4 power on reset ovp/otp gone rst vfault(clamp) vfault(otp) vfault(ovp) iotp vdd drv rfault(clamp) 600 ns time constant 1 blanking time s falling edge as a matter of fact, the controller operates normally while the fault pin voltage is maintained within the upper and lower fault thresholds. upper and lower fault detectors have blanking delays to prevent noise from triggering them. both ovp and otp comparator output are validated only if its high-state duration lasts a minimum of 600 ns. below this value, the event is ignored. then, a counter ensures that ovp/otp events occurred for 4 successive drive clock pulses before actually latching the part. when the part is latched-off, the drive is immediately turned off and v cc goes in endless hiccup mode. the power supply needs to be un-plugged to reset the part (v cc(reset) or bo event). please note that this protection on the fault pin is autorecovery for the e version. auto-recovery short-circuit protection in case of output short-circuit or if the power supply experiences a severe overloading situation, an internal error flag is raised and starts a countdown timer. if the flag is asserted longer than the timer?s programmed value, the driving pulses are stopped and a 1-s auto-recovery timer starts. if v cc voltage is below v cc(min) , hv current source is activated to build up the voltage to v cc(on) . on the contrary, if v cc voltage is above v cc(min) , hv current source is not activated, v cc falls down as the auxiliary pulses are missing and the controller waits that v cc(min) is crossed to enable the stat-up current source. during the timer count down, the controller purposely ignores the re-start when v cc crosses v cc(on) and waits for another v cc cycle. by lowering the duty cycle in fault condition, it naturally reduces the average input power and the rms current in the output cable. illustration of such principle appears in figure 39. please note that soft-start is activated upon re-start attempt. ncp1239 www.onsemi.com 21 figure 39. an auto-recovery hiccup mode is entered in case a faulty event longer than 64 ms is acknowledged by the controller autorecovery timer v cc(on) v cc(off) v cc(min) overload on the output voltage ocp timer v cc (t) t v drv (t) no pulse area autorecovery timer ocp timer t the hiccup is operating regardless of the brown-out level. however, when the internal comparator toggles indicating that the controller recovers from a brown-out situation (the input line was ok, then too low and back again to normal), the hiccup is interrupted and the controller re-starts to the next available v cc(on) . figure 40 displays the resulting waveform: the controller is protecting the converter against an overload. the mains suddenly went down, and then back again at a normal level. right at this moment, the hiccup logic receives a reset signal and ignores the next hiccup to immediately initiate a re-start signal. figure 40. bo event in auto-recovery or latch mode autorecovery timer v cc(on) v cc(off) v cc(min) overload on the output voltage ocp timer v cc (t) t v drv (t) no pulse area bo(t) bo_ok = "0" bo_ok = "1" bo_ok = "1" t t ncp1239 www.onsemi.com 22 latched short circuit protection with pre-short in some applications, the controller must be fully latched in case of an output short circuit presence. when the error flag is asserted, meaning the controller is asked to deliver its full peak current, upon timer completion, the controller latches off: all pulses are immediately stopped and v cc hiccups between the two levels, v cc(on) and v cc(min) . however, in presence of a small v cc capacitor, it can very well be the case where the stored energy does not give enough time to let the timer elapse before v cc touches the v cc(off) . when this happens, the latch is not acknowledged since the timer countdown has been prematurely aborted. to avoid this problem, ncp1239 combines the error flag assertion together with the uvlo flag: upon start up, as maximum p ower is asked to increase v out , the error flag is temporarily raised until regulation is met. if during the time the flag is raised an uvlo event is detected, the part latches off immediately. when latched, v cc hiccups between the two levels, v cc(on) and v cc(min) until a reset occurs (brown-out event or v cc cycled down below v cc(reset) ). in normal operation, if a uvlo event is detected for any reason while the error flag is not asserted, the controller will naturally resume operations. please also note that this pre-short protection is activated only during start-up sequence. in normal operation, even if an uvlo event occurs while the error flag is asserted, the controller will enters in auto-recovery mode. details of this behavior are given in figure 41. figure 41. uvlo event during start-up sequence and in normal operation new sequence uvlo and ocp flag at start? up latched resumed glitch or overloa d o cp flag 0 1 reset fb ok t t t v cc(on) v cc(off) v cc(min) v cc (t) v drv (t) latching or auto-recovery mode the b, c, d and e versions are auto-recovery. when an overload fault is detected, they stop generating drive pulses and v cc hiccups between v cc(min) and v cc(on) during the auto-recovery timer before initiate a fresh start-up sequence with soft-start. the a, f, g, h and i versions latch off when they detect an overload situation. in this condition, the circuit stops generating drive pulses and let v cc drop down. when v cc has reached 10-v cc(min) level, the circuit charged up v cc to v cc(on) . the controller enters in an endless hiccup mode. the device cannot recover operation until v cc drops below v cc(reset) or brownout recovery signal is applied. practically, the power supply must be unplugged to be reset (v cc off s off r sense (eq. 15) 133 m 0.33 44 mv s 50% of this value is 22 mv/ s. the internal slope compensation level is typically 29 mv/ s (for the 65-khz version) so it will nicely compensate this design example. what if my converter is under compensated? you can still add compensation ramp via a simple rc arrangement showed in figure 43. please look at and8029 available from www.onsemi.com regarding calculation details of this configuration. ncp1239 www.onsemi.com 24 figure 43. an easy means to add slope compensation is by using an extra rc network building a ramp from the drive signal r1 c1 d1 1n4148 rsense r3 drv cs r4 a 2 nd over-current comparator for abnormal over-current fault detection a severe fault like a winding short-circuit can cause the switch current to increase very rapidly during the on-time. the current sense signal significantly exceeds v ilim1 . but, because the current sense signal is blanked by the leb circuit during the switch turn on, the power switch current can become huge causing system damage. the ncp1239 protects against this fault by adding an additional comparator for abnormal over-current fault detection. the current sense signal is blanked with a shorter leb duration, t leb2 , typically 120 ns, before applying it to the abnormal over-current fault comparator. the voltage threshold of the comparator, v ilim2 , typically 1.2 v, is set 50 % higher than v limit1 , to avoid interference with normal operation. four consecutive abnormal over-current faults cause the controller to enter latch mode. the count to 4 provides noise immunity during surge testing. the counter is reset each time a drv pulse occurs without activating the fault over-current comparator. please note that like timer-based short-circuit protection, a, f, g, h and i versions are latching off compared to b, c, d and e versions that are auto-recovery. over-voltage protection on v cc pin the ncp1239 hosts a dedicated comparator on the v cc pin. when the voltage on this pin exceeds 25.5 v typically (32.0 v for f versions) for more than 20 s, a signal is sent to the internal latch and the controller immediately stops the driving pulses while remaining in a lockout state. depending controller options, this ovp on v cc pin can be auto-recovery or latched. for latching-off versions, the part can be reset by cycling down its v cc , for instance by pulling off the power plug but also if a brown-out recovery is sensed by the controller. this technique offers a simple and cheap means to protect the converter against optocoupler. protecting from a failure of the current sensing a 1- a (typically) pull-up current source, i cs , pulls up the cs pin to disable the controller if the pin is left open. in addition the maximum duty ratio limit (80% typically) avoids that the mosfet stays permanently on if the switch current cannot reach the setpoint when for instance, the input voltage is low or if the cs pin is grounded. in this case, the ocp timer is activated. if the timer elapses, the controller enters in auto-recovery or endless hiccup mode depending on the controller option. this unexpected operation can lead to deep ccm with destructive consequences. ncp1239 www.onsemi.com 25 soft-start soft-start is achieved by ramping up an internal reference, v sstart , and comparing it to current sense signal. v sstart ramps up from 0 v once the controller powers up. the setpoint rise is then limited by the v sstart ramp so that a gradual increase of the power switch current during start-up. the soft-start duration (that is, the time necessary for the ramp to reach the v ilim1 steady state current limit), t sstart , is typically 8 ms. driver the ncp1239 maximum supply voltage, v cc(max) , is 25.5 v (32.0 v for f versions). typical high-voltage mosfets have a maximum gate-source voltage rating of 20 v. the drv pin incorporates an active voltage clamp to limit the gate voltage on the external mosfets. the drv voltage clamp, v drv(high) is typically 13.5 v with a maximum limit of 16 v. thermal shutdown an internal thermal shutdown circuit monitors the junction temperature of the ic. the controller is disabled if the junction temperature exceeds the thermal shutdown threshold, t shdn , typically 150 c. a continuous v cc hiccup is initiated after a thermal shutdown fault is detected. the controller restarts at the next v cc(on) once the ic temperature drops below below t shdn by the thermal shutdown hysteresis, t shdn(hys) , typically 20 c. the thermal shutdown is also cleared if v cc drops below v cc(reset) or a brown-out fault is detected. a new power up sequences commences at the next v cc(on) once all the faults are removed. table 5. ordering information device marking freq. ocp protection v cc ovp protection fault pin protection bo levels package shipping ? ncp1239ad65r2g 1239a065 65 khz latch latch latch 110/101 soic?7 (pb-free ) 2500 / tape & reel ncp1239bd65r2g 1239b065 65 khz auto-recovery latch latch 110/101 ncp1239cd65r2g 1239c065 65 khz auto-recovery auto-recovery latch 110/101 ncp1239dd65r2g 1239d065 65 khz auto-recovery latch latch 101/95 ncp1239ed65r2g 1239e065 65 khz auto-recovery auto-recovery auto-recovery 110/101 ncp1239fd65r2g 1239f065 65 khz latch latch latch 229/176 ncp1239hd65r2g 1239h065 65 khz latch latch latch 229/224 ncp1239id65r2g 1239i065 65 khz latch latch latch 101/95 ncp1239ad100r2g 1239a100 100 khz latch latch latch 110/101 ncp1239bd100r2g 1239b100 100 khz auto-recovery latch latch 110/101 NCP1239ED100R2G 1239e100 100 khz auto-recovery auto-recovery auto-recovery 110/101 ncp1239gd100r2g 1239g100 100 khz latch latch latch 95/86 ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. ncp1239 www.onsemi.com 26 package dimensions soic?7 case 751u issue e seating plane 1 4 5 8 r j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b are datums and t is a datum surface. 4. dimension a and b do not include mold protrusion. 5. maximum mold protrusion 0.15 (0.006) per side. s d h c dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ?a? ?b? g m b m 0.25 (0.010) ?t? b m 0.25 (0.010) t s a s m 7 pl 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does o n semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including ?typic als? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the right s of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semicondu ctor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distrib utors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 ncp1239/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative ? |
Price & Availability of NCP1239ED100R2G
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |